1. Field of the Invention
The present invention relates to a semiconductor memory device circuit and, more particularly, to a column select control circuit in a semiconductor memory device which controls the column select line enable time according to the selected refresh mode.
2. Description of the Related Art
Generally, a volatile semiconductor memory device such as a dynamic random access memory (DRAM) stores data by accumulating a charge in the capacitor of a memory cell. DRAM devices are widely used in data processing systems. DRAM devices include circuits for reading the data stored in the memory cell by amplifying the memory cell signal and recharging the memory cell before the data is lost due to leakage currents in the cell capacitor. The process of recharging the memory cell is termed refresh.
Moreover, DRAM devices having faster operating speeds are highly desirable. In order to obtain faster DRAM devices, it is necessary to reduce the access time by reducing the transition interval of the row address strobe signal access time tRAC. So long as the data sensing operation is not affected by ensuring the minimum charge sharing and sensing intervals between the memory cell and the corresponding bit line, increasing the speed of the row address strobe signal access time tRAC leads to higher DRAM operating speeds.
The trend in the semiconductor memory device industry is for devices that have higher integration, lower power consumption, faster operating speeds, multiple functions, and configurability such that a single device can meet the various demands of system designers. In certain instances, many modes are designed on one chip, each mode capable of selection by a simple subsequent process. One widely used method of selecting among a variety of modes is through the use of fuses. The desired mode is selected by fuse trimming just before the die goes through the package assembly process. However, problems arise when many modes are designed on one chip. For example, a 4K refresh mode has a better sensing performance than a 1K refresh mode because the former has a remarkably smaller power to ground voltage (VCC/VSS) noise ratio. Therefore, the row address strobe signal access time tRAC can be improved by enabling the column select line (CSL) sooner in the 4K refresh mode. However, the conventional design does not vary the column select path when either the 1K or 4K refresh mode is selected. Therefore, the speed of the row address strobe signal access time tRAC is the same for both the 4K and tie 1K refresh modes. In other words, even though the 4K refresh mode can improve the speed of the row address strobe signal access time tRAC, the row address strobe signal access time tRAC has the same speed in both the 1K and 4K refresh modes. This problem is even more severe in the 8K refresh mode becoming one of the primary reasons for dissatisfaction among system designers and users.
Consequently, the speed of the row address strobe signal access time tRAC is not improved even though various refresh modes having improved speeds are provided on one chip because the column select line is enabled through the same column select enable path for all of the refresh modes.